A Programmable Continuous-Time Floating-Gate Fourier Processor
نویسندگان
چکیده
We present a programmable continuous-time floating-gate Fourier processor that decomposes the incoming signal into frequency bands by analog bandpass filters, multiplies each channel by a nonvolitile weight, and then recombines the frequency channels. A digital signal processor would take a similar approach of computing a fast Fourier transform (FFT), multiplying the frequency components by a weight and then computing an inverse FFT. We decompose the frequency bands of the incoming signal using the transistor-only version of the autozeroing floating-gate amplifier (AFGA), also termed the capacitively coupled current conveyer (C). Each band decomposition is then fed through a floating-gate multiplier to perform the band weighting. Finally, the multiplier outputs are summed using Kirchoff current law to give a band-weighted output of the original signal. We examine many options to reduce second-order harmonic problems inherent in the single-sided C. We present a method for programming arrays of floating-gate devices that are used in the weighting of the bands. All of these pieces fit together to form an elegant and systematic Fourier processor.
منابع مشابه
Design and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag (TECHNICAL NOTE)
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...
متن کاملAn ultra-high-speed FPGA based digital correlation processor
This paper presents an ultra-high-speed correlation processor for FPGA (Field-Programmable Gate Array) which is based on MDF (multiplepath delay feedback) pipelined FFT (fast Fourier transform) architecture. In order to decrease the resource cost and processing delay, the FFT processor is based on DIF (Decimation in Frequency) decomposition method, and the IFFT processor is based on DIT (Decima...
متن کاملA Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform
This paper presents the design and implementation of the Discrete Fourier Transform@FT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive a * Consequently, the eventual goal of this work is to enhance the execution ofa floating-point precision DFT algorithm by off loading the algorithm from the...
متن کاملAn FPGA-based Floating Point Unit for Rounding Error Analysis
Detection of floating-point rounding errors normally requires run-time analysis in order to be effective and software-based tools are seldom used due to the extremely high computational demands. In this paper we present a field programmable gate array (FPGA) based floating-point coprocessor which supports standard IEEE-754 arithmetic, user selectable precision and Monte Carlo Arithmetic (MCA). ...
متن کاملASIC Implementation of High Speed Processor for Calculating Discrete Fourier Transformation using Circular Convolution Technique
The improvement in speed and power for calculating discrete Fourier transformation using circular convolution is well established, but all the work so far been reported are at FPGA (gate) level. In this paper ASIC implementation of high speed processor for calculating Discrete Fourier Transformation (DFT) based on circular convolution architectures is reported for the first time. The IEEE-754 s...
متن کامل